Click Here for!NCEE-2016 at ALIET on 22nd March 2016 All the Submitted Papers are Uploaded & Avilable at Special Issue-2016

INTERNATIONAL JOURNAL OF RESEARCH IN ELECTRONICS & COMMUNICATION ENGINEERING Mar - Apr 2017(VOLUME-5,ISSUE-2)

S.NOTITLE OF MANUSCRIPTARTICLE IDDOWNLOAD
1FM0 and Manchester Encoding Techniques with Clock Gating Technique
B.Raghu, B.Umasankar
IJRECE/V5/2-2301Download
2Implementation of Edge Detection Process Using Sobel Operator on FPGA
T.Salam, T.Renushyapale
IJRECE/V5/2-2302Download
3Featured Reversible BCD Adder and Its Advance Implementation
K.Tejaswini, Ch.Srinivasa Kumar
IJRECE/V5/2-2303Download
4Application Oriented Test Pattern Generation for BIST
P.Anupama, V.Sulochana
IJRECE/V5/2-2304Download
5Error Protection Scheme for Parallel Filters
T.Sundhya, K.ChandraRao
IJRECE/V5/2-2305Download
6An Efficient and High Performed MAC Unit
S.Lavanya Kumari,Sk.Sahir
IJRECE/V5/2-2306Download
7Smart Electricity Meter Data Intelligence for Future Energy System
Shaik.Mahaboob Subhani, K.Santhi
IJRECE/V5/2-2307Download
8Image Denoising Using NSCT with Image Fusion and Post Processing Technique
K.SrinivasaRao, P.N.S SaiSudha, G.SaiSravanthi, Ch.Sirisha
IJRECE/V5/2-2308Download
9A Novel Approach for Alternative Phase Shift Based PWM for DC-DC Converter with Grid Connected Power System
Sayyed.Abdulsalam, Dr.Akbar Khan
IJRECE/V5/2-2309Download
10Performance Analysis of Line and Character Segmentation for Different Language Text Images
M.Rama Krishna, K.Srinivasa Rao, P.ArunaKumari, P.Ramya Sri, T.Aishwarya
IJRECE/V5/2-2310Download
11A Highly Secure Video Steganography Using DWT
Abdul Azeem, K.Sobhita, P.Bhavya Deepika, G.Hepsiba, T.Akshaya
IJRECE/V5/2-2311Download
12Performance and Power Efficient Targeted Multiplier for Tiny Nodes
S.Sudha Rani, A.SomaSekhar
IJRECE/V5/2-2312Download
13Design of Amended Reversible LFSR
Gongati Srikanth Reddy, G.Subash
IJRECE/V5/2-2313Download
14Generalized MAC Unit Design by Using Reversible Logic
Gandam Surendra Babu, G.Subash
IJRECE/V5/2-2314Download
15Implementing Phase Locked Loop Using VLSI Technology
Bala Srinivas Peteti,Krishna Saladi
IJRECE/V5/2-2315Download
16Design of Fir Filter Based Weight Pattern Generator Using LP-LFSR
Kalaga V. Kiranmayee Iswarya, Mr.D.V.Ramakrushna
IJRECE/V5/2-2316Download